dbcve.org
Cortex A710 FirmwareOperating system · Arm

CVE-2024-5660

CRITICAL · 9.8 CVSS v3.1 Published 2024-12-10
Mitigation only
No fix yet — a mitigation exists. There is no fixed release. A documented workaround reduces exposure in the meantime.
See remediation →
100/100
Remediation priority · Urgent
Remotely reachable No privileges Zero-click

Official description Straight from the sourceThe vendor's or NVD's own wording, published unedited. Authoritative, but often terse — it says what broke, rarely what to do.

NVD · unedited
Use of Hardware Page Aggregation (HPA) and Stage-1 and/or Stage-2 translation on Cortex-A77, Cortex-A78, Cortex-A78C, Cortex-A78AE, Cortex-A710, Cortex-X1, Cortex-X1C, Cortex-X2, Cortex-X3, Cortex-X4, Cortex-X925, Neoverse V1, Neoverse V2, Neoverse V3, Neoverse V3AE, Neoverse N2 may permit bypass of Stage-2 translation and/or GPT protection.

Technical summary Written by usOur analysis, written from the advisory, the CVSS vector and the affected-version data. It adds context the advisory leaves out, and never invents facts that are not in the source.

dbcve analysis · high confidence

This is a hardware vulnerability in specific ARM Cortex-A and Neoverse processor cores where the use of Hardware Page Aggregation (HPA) combined with Stage-1 and/or Stage-2 memory translation can allow an attacker to bypass Stage-2 translation boundaries (used in virtualization) and Granular Protection Table (GPT) memory protections, potentially enabling escape from isolated execution environments.

MitigationApply microcode/firmware updates from ARM and device manufacturers; if unavailable, consider disabling HPA features or implementing additional software-based memory isolation layers as a compensating control.

Verify against the referenced sources before acting — the references below are authoritative for this CVE, this summary is not.

Affected products & versions What the vendor confirmedThe version ranges the vendor confirmed as vulnerable. If your version sits inside a range here, treat yourself as exposed until you have upgraded.

NVD · CPE data
Cortex A710 FirmwareOperating system
Affected:all versions
Cortex A77 FirmwareOperating system
Affected:all versions
Cortex A78 FirmwareOperating system
Affected:all versions
Cortex A78ae FirmwareOperating system
Affected:all versions
Cortex A78c FirmwareOperating system
Affected:all versions
Cortex X1 FirmwareOperating system
Affected:all versions
Cortex X1c FirmwareOperating system
Affected:all versions
Cortex X2 FirmwareOperating system
Affected:all versions

CVSS breakdown How the score is builtThe industry scoring standard. It rates how the flaw is reached, what it takes to exploit, and what an attacker gains — the score is derived from those, not the other way round.

From the vector
Attack vector
Network
Complexity
Low
Privileges
None
User interaction
None
Scope
Unchanged
Confidentiality
High
Integrity
High
Availability
High

CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:H/A:H

Am I affected? How to checkSteps we derive from the advisory and the affected-version data, so you can decide whether this CVE reaches your setup. They are a guide, not a scan — your own configuration is the authority.

dbcve checks

Work through these to decide whether this CVE applies to you.

  1. Identify the ARM processor model
    Check the system's processor information using commands such as 'lscpu', 'cat /proc/cpuinfo', or system firmware/dmesg logs to identify the exact ARM Cortex core model
    Affected if The system does not have an ARM Cortex-A710, A77, A78, A78ae, A78c, X1, X1c, or X2 core - if a different or non-affected ARM core is present, this vulnerability does not apply
  2. Check if Hardware Page Aggregation (HPA) is enabled
    Examine system firmware/UEFI settings, ARM-specific registers (such as MAIR_ELx or TTBR0_EL1/TTBR1_EL1 page table configuration), or hypervisor configuration for HPA-related settings. Consult vendor documentation for the specific method to inspect HPA status on the affected hardware
    Affected if HPA is disabled or not implemented on the system - the vulnerability only applies when HPA is actively enabled in the memory translation configuration
  3. Verify if Stage-2 memory translation is in use
    Check if virtualization is enabled on the system. Look for hypervisor presence via 'lscpu' (Hypervisor column), 'systemd-detect-virt', or by examining hypervisor-specific configurations and logs. Stage-2 translation is used by hypervisors for second-stage address translation in virtual machines
    Affected if The system does not use virtualization (no hypervisor/Stage-2 translation) AND does not use Granular Protection Tables (GPT) - the vulnerability requires one of these protection mechanisms to be in place for the bypass to have impact
  4. Confirm firmware version for inventory
    Query the system firmware version through vendor-specific tools (e.g., 'dmidecode' on systems that support it, or vendor-provided firmware inspection utilities) to document the current baseline
    Affected if All firmware versions of the affected cores are vulnerable - this check is for inventory and verification purposes rather than determining specific vulnerable versions

The system is affected if it contains any of the listed ARM Cortex cores (A710, A77, A78, A78ae, A78c, X1, X1c, X2) AND has Hardware Page Aggregation (HPA) enabled while using virtualization (Stage-2 translation) or Granular Protection Tables (GPT).

Generated from the published advisory. Verify against your own configuration.

Check your environment

Paste your version and any relevant configuration and it will be compared against the affected criteria above. Do not include secrets or credentials.

AI-assisted, checked against the advisory. Informational, not a guarantee.

Remediation Closing itWhat it takes to close this. Where a vendor fix exists we point at it; where none exists we say so plainly, and can build one. Effort estimates are scoped from the advisory, not from your codebase.

From vendor data
Mitigation available No clean upgrade yet — mitigate in the meantime
Mitigation

Apply microcode/firmware updates from ARM and device manufacturers; if unavailable, consider disabling HPA features or implementing additional software-based memory isolation layers as a compensating control.

Fix this in Cortex A710 Firmware Scoped from the published advisory
  • Consultation16.0 h
  • Implementation40.0 h
  • Testing24.0 h
  • Review / QA12.0 h
92.0 hours of engineering $16,160
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References Go to the primary sourcePrimary sources — vendor advisories, patches and trackers. Where our summary and a reference disagree, the reference wins.

Primary sources

Practitioner notes

Contributed

Peer-ranked notes from engineers who’ve handled CVE-2024-5660 in production — separate from our analysis above.

No notes yet

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What this is

A place for practitioners to share what actually worked: a mitigation you’ve tested, a configuration change, a version- or environment-specific caveat, or a link to a verified patch. The most useful notes rise to the top as peers upvote them, so the signal stays high.

What belongs here
  • Verified mitigations, workarounds, and config changes
  • Version or environment caveats, and links to real fixes
  • No weaponised exploit code, or anything meant to cause harm
  • No spam, self-promotion, credentials, or personal data