dbcve.org
C1 Ultra FirmwareOperating system · Arm

CVE-2025-0647

HIGH · 7.9 CVSS v3.1 Published 2026-01-14
Mitigation only
No fix yet — a mitigation exists. There is no fixed release. A documented workaround reduces exposure in the meantime.
See remediation →
81/100
Remediation priority · High
Zero-click

Official description Straight from the sourceThe vendor's or NVD's own wording, published unedited. Authoritative, but often terse — it says what broke, rarely what to do.

NVD · unedited
In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.

Technical summary Written by usOur analysis, written from the advisory, the CVSS vector and the affected-version data. It adds context the advisory leaves out, and never invents facts that are not in the source.

dbcve analysis · moderate confidence

A hardware vulnerability in certain Arm CPUs allows a CPP RCTX instruction to inhibit TLB (Translation Lookaside Buffer) invalidation when a TLBI is issued. This causes the affected Processing Element to retain stale TLB entries that should have been invalidated, potentially leading to memory consistency issues or information disclosure.

MitigationContact Arm and your hardware vendor for microcode/firmware updates addressing this CPU flaw. Inventory affected systems and apply vendor-supplied patches; if no update is available, consider hardware replacement or implement software-based workarounds such as explicit TLB management where feasible.

Verify against the referenced sources before acting — the references below are authoritative for this CVE, this summary is not.

Affected products & versions What the vendor confirmedThe version ranges the vendor confirmed as vulnerable. If your version sits inside a range here, treat yourself as exposed until you have upgraded.

NVD · CPE data
C1 Ultra FirmwareOperating system
Affected:all versions
C1 Premium FirmwareOperating system
Affected:all versions
Cortex A710 FirmwareOperating system
Affected:all versions
Cortex X2 FirmwareOperating system
Affected:all versions
Cortex X3 FirmwareOperating system
Affected:all versions
Cortex X4 FirmwareOperating system
Affected:all versions
Cortex X925 FirmwareOperating system
Affected:all versions
Neoverse V2 FirmwareOperating system
Affected:all versions

CVSS breakdown How the score is builtThe industry scoring standard. It rates how the flaw is reached, what it takes to exploit, and what an attacker gains — the score is derived from those, not the other way round.

From the vector
Attack vector
Local
Complexity
Low
Privileges
High
User interaction
None
Scope
Changed
Confidentiality
High
Integrity
High
Availability
None

CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:N

Am I affected? How to checkSteps we derive from the advisory and the affected-version data, so you can decide whether this CVE reaches your setup. They are a guide, not a scan — your own configuration is the authority.

dbcve checks

Work through these to decide whether this CVE applies to you.

  1. Identify the Arm CPU model in the system
    On the target system, run: cat /proc/cpuinfo on Linux or check system information via IPMI/BMC. Look for the CPU implementer and part number in the flags or model name fields.
    Affected if The CPU model matches one of: Arm C1 Ultra, C1 Premium, Cortex A710, Cortex X2, Cortex X3, Cortex X4, X925, or Neoverse V2
  2. Check the CPUID or hardware identification
    Use commands like 'lscpu' or read from /sys/devices/system/cpu/cpu0/cpuid to get the exact CPU part number. Cross-reference with Arm's product documentation to confirm the specific SKU variant.
    Affected if The CPU part number corresponds to any of the affected firmware variants listed in the CVE
  3. Query firmware or microcode version
    Check BMC/IPMI for firmware version information, or use 'cat /sys/class/dmi/id/*' on Linux systems. On Arm servers, check the ARM Trusted Firmware version via 'cat /sys/firmware/arm_tee/menu' or vendor-specific tools.
    Affected if The firmware version has not been updated to include the microcode fix from Arm (contact Arm or your vendor for the fixed version)
  4. Determine if TLBI operations are in use
    This is a hardware-level issue. If running virtualization or OS-level software that performs explicit TLB management, review software logs for TLB-related consistency errors or cache coherency issues.
    Affected if The system exhibits unexplained memory consistency errors or information disclosure that cannot be otherwise explained, and the CPU is in the affected list

The system is affected if it contains any of the listed Arm CPU models (C1 Ultra, C1 Premium, Cortex A710, Cortex X2, Cortex X3, Cortex X4, X925, or Neoverse V2) and the firmware has not been updated to the patched version provided by Arm or the hardware vendor.

Generated from the published advisory. Verify against your own configuration.

Check your environment

Paste your version and any relevant configuration and it will be compared against the affected criteria above. Do not include secrets or credentials.

AI-assisted, checked against the advisory. Informational, not a guarantee.

Remediation Closing itWhat it takes to close this. Where a vendor fix exists we point at it; where none exists we say so plainly, and can build one. Effort estimates are scoped from the advisory, not from your codebase.

From vendor data
Mitigation available No clean upgrade yet — mitigate in the meantime
Mitigation

Contact Arm and your hardware vendor for microcode/firmware updates addressing this CPU flaw. Inventory affected systems and apply vendor-supplied patches; if no update is available, consider hardware replacement or implement software-based workarounds such as explicit TLB management where feasible.

Fix this in C1 Ultra Firmware Scoped from the published advisory
  • Consultation8.0 h
  • Implementation16.0 h
  • Testing12.0 h
  • Review / QA4.0 h
40.0 hours of engineering $7,000
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References Go to the primary sourcePrimary sources — vendor advisories, patches and trackers. Where our summary and a reference disagree, the reference wins.

Primary sources

Practitioner notes

Contributed

Peer-ranked notes from engineers who’ve handled CVE-2025-0647 in production — separate from our analysis above.

No notes yet

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What this is

A place for practitioners to share what actually worked: a mitigation you’ve tested, a configuration change, a version- or environment-specific caveat, or a link to a verified patch. The most useful notes rise to the top as peers upvote them, so the signal stays high.

What belongs here
  • Verified mitigations, workarounds, and config changes
  • Version or environment caveats, and links to real fixes
  • No weaponised exploit code, or anything meant to cause harm
  • No spam, self-promotion, credentials, or personal data