CVE-2025-45006
Official description Straight from the sourceThe vendor's or NVD's own wording, published unedited. Authoritative, but often terse — it says what broke, rarely what to do.
NVD · uneditedImproper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.
Technical summary Written by usOur analysis, written from the advisory, the CVSS vector and the affected-version data. It adds context the advisory leaves out, and never invents facts that are not in the source.
dbcve analysis · high confidenceThe Open-Source RISC-V Processor (commit f517abb) incorrectly retains the mstatus.SUM bit in a non-zero state, violating RISC-V Privileged Specification constraints. The SUM bit controls whether User mode can access Supervisor mode pages; improper retention allows User-mode code to potentially read/write physical memory that should be protected by the MMU, enabling privilege escalation and physical memory access attacks.
Verify against the referenced sources before acting — the references below are authoritative for this CVE, this summary is not.
CVSS breakdown How the score is builtThe industry scoring standard. It rates how the flaw is reached, what it takes to exploit, and what an attacker gains — the score is derived from those, not the other way round.
From the vector- Attack vector
- Network
- Complexity
- Low
- Privileges
- None
- User interaction
- None
- Scope
- Unchanged
- Confidentiality
- High
- Integrity
- None
- Availability
- High
CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:H
Am I affected? How to checkSteps we derive from the advisory and the affected-version data, so you can decide whether this CVE reaches your setup. They are a guide, not a scan — your own configuration is the authority.
dbcve checksWork through these to decide whether this CVE applies to you.
-
Identify your RISC-V processorRun 'cat /proc/cpuinfo' or check the device tree (cat /proc/device-tree/compatible) to determine the processor model and vendorAffected if The system uses an open-source RISC-V processor core (e.g., Rocket Chip, Berkeley Out-of-Order Machine, or similar) that may have this flaw
-
Check the RISC-V privilege architecture versionExamine documentation or run 'riscv64-unknown-elf-gcc -v' to identify the privilege spec version your software targetsAffected if The implementation follows a RISC-V privileged spec version prior to the fix for mstatus.SUM bit handling
-
Read the mstatus register SUM bitUsing a privileged instruction (CSRR) or debug interface, read the mstatus register and inspect bit 18 (SUM bit) - for example, via 'rdinstret' or a debug probe reading mstatusAffected if The SUM bit (mstatus[18]) is observed to be non-zero when it should be zero after a privilege mode transition
-
Test SUM bit behavior on mode transitionWrite a test that transitions from Supervisor (S) mode to User (U) mode and verify whether the SUM bit is properly cleared or incorrectly retainedAffected if After returning from S-mode to U-mode, the SUM bit remains set when it should have been cleared per RISC-V privileged specification
-
Check vendor security advisoriesSearch for CVE-2025-45006 or 'mstatus.SUM' in your processor vendor's security advisory database or firmware release notesAffected if The vendor has published an advisory acknowledging this issue for your processor model
You are affected if you are running an open-source RISC-V processor where the mstatus.SUM bit is retained (non-zero) after transitioning from Supervisor to User mode, instead of being cleared as required by the RISC-V privileged specification.
Generated from the published advisory. Verify against your own configuration.
Remediation Closing itWhat it takes to close this. Where a vendor fix exists we point at it; where none exists we say so plainly, and can build one. Effort estimates are scoped from the advisory, not from your codebase.
From vendor dataThis is a hardware/processor RTL bug requiring a fix in the core's privileged architecture implementation to properly clear mstatus.SUM on appropriate context switches (e.g., mret). Deployments using affected cores must coordinate with the processor vendor for core update or microcode patch if available.
- Consultation12.0 h
- Implementation24.0 h
- Testing48.0 h
- Review / QA16.0 h
An estimate, not a bill — we confirm scope with you before any work starts. Need it this week? Rush from $26,880.
Scan for this in your stack
Free · runs locallyCheck whether your project pulls in CVE-2025-45006 — or any other known-vulnerable package — straight from your lock files. Free and open source; it runs locally and uploads nothing.
References Go to the primary sourcePrimary sources — vendor advisories, patches and trackers. Where our summary and a reference disagree, the reference wins.
Primary sourcesPractitioner notes
ContributedPeer-ranked notes from engineers who’ve handled CVE-2025-45006 in production — separate from our analysis above.
The advisory tells you what broke. It rarely tells you what actually worked. If you’ve dealt with this one, that detail is what the next engineer is searching for.
- The version that genuinely resolved it — not the one the vendor claimed
- A config change or rule that shut the vector down
- A gotcha in the upgrade path that cost you an afternoon
No notes yet
Be the first to add a field note for this CVE — a mitigation you’ve verified, a version caveat, or a link to a working fix. Sign in above to contribute.
A place for practitioners to share what actually worked: a mitigation you’ve tested, a configuration change, a version- or environment-specific caveat, or a link to a verified patch. The most useful notes rise to the top as peers upvote them, so the signal stays high.
- Verified mitigations, workarounds, and config changes
- Version or environment caveats, and links to real fixes
- No weaponised exploit code, or anything meant to cause harm
- No spam, self-promotion, credentials, or personal data