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Linux KernelOperating system · Linux

CVE-2026-53354

HIGH · 8.8 CVSS v3.1 Published 2026-07-01
Fix available
A fix is available. Upgrade to 5.10.259 / 5.15.210 or later.
See remediation →
90/100
Remediation priority · Urgent
Zero-click 7 weeks old

Official description Straight from the sourceThe vendor's or NVD's own wording, published unedited. Authoritative, but often terse — it says what broke, rarely what to do.

NVD · unedited
In the Linux kernel, the following vulnerability has been resolved: arm64: errata: Mitigate TLBI errata on various Arm CPUs A number of CPUs developed by Arm suffer from errata whereby a broadcast TLBI;DSB sequence may complete before the global observation of writes which are translated by an affected TLB entry. These errata ONLY affect the completion of memory accesses which have been translated by an invalidated TLB entry, and these errata DO NOT affect the actual invalidation of TLB entries. TLB entries are removed correctly. This issue has been assigned CVE ID CVE-2025-10263. To mitigate this issue, Arm recommends that software follows any affected TLBI;DSB sequence with an additional TLBI;DSB, which will ensure that all memory write effects affected by the first TLBI have been globally observed. The additional TLBI can use any operation that is broadcast to affected CPUs, and the additional DSB can use any option that is sufficient to complete the additional TLBI. The ARM64_WORKAROUND_REPEAT_TLBI workaround is sufficient to mitigate the issue. Enable this workaround for affected CPUs, and update the silicon errata documentation accordingly. Note that due to the manner in which Arm develops IP and tracks errata, some CPUs share a common erratum number.

Technical summary Written by usOur analysis, written from the advisory, the CVSS vector and the affected-version data. It adds context the advisory leaves out, and never invents facts that are not in the source.

dbcve analysis · high confidence

This is a hardware erratum in Arm CPUs where a broadcast TLBI;DSB (TLB Invalidate;Data Synchronization Barrier) sequence may complete before writes translated by an invalidated TLB entry are globally observed, potentially causing memory coherence issues. The Linux kernel provides the ARM64_WORKAROUND_REPEAT_TLBI workaround that adds an extra TLBI;DSB pair to ensure proper memory ordering. The fix requires enabling this workaround for affected CPU variants in the kernel's errata handling code.

MitigationEnable the ARM64_WORKAROUND_REPEAT_TLBI kernel workaround for affected Arm CPU models by updating the CPU errata detection logic in the Linux kernel, along with updating associated silicon errata documentation.

Verify against the referenced sources before acting — the references below are authoritative for this CVE, this summary is not.

Affected products & versions What the vendor confirmedThe version ranges the vendor confirmed as vulnerable. If your version sits inside a range here, treat yourself as exposed until you have upgraded.

NVD · CPE data
Linux KernelOperating system
Affected:>= 3.7, < 5.10.259>= 5.11, < 5.15.210>= 5.16, < 6.1.176>= 6.2, < 6.6.143>= 6.7, < 6.12.94>= 6.13, < 6.18.36>= 6.19, < 7.0.13>= 7.1, < 7.1.1

CVSS breakdown How the score is builtThe industry scoring standard. It rates how the flaw is reached, what it takes to exploit, and what an attacker gains — the score is derived from those, not the other way round.

From the vector
Attack vector
Local
Complexity
Low
Privileges
Low
User interaction
None
Scope
Changed
Confidentiality
High
Integrity
High
Availability
High

CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:H

Am I affected? How to checkSteps we derive from the advisory and the affected-version data, so you can decide whether this CVE reaches your setup. They are a guide, not a scan — your own configuration is the authority.

dbcve checks

Work through these to decide whether this CVE applies to you.

  1. Identify the Arm CPU model
    Run 'cat /proc/cpuinfo' on Linux or check system firmware/dmesg for CPU part number or implementer details (e.g., ARM implementer ID and variant)
    Affected if CPU is an Arm processor whose model falls within the errata-affected range and lacks the fix
  2. Check kernel version
    Run 'uname -r' to get the kernel version, then check if it includes the ARM64_WORKAROUND_REPEAT_TLBI fix (generally kernel 6.x and later may include it, but check release notes)
    Affected if Kernel version predates the errata fix being merged
  3. Verify kernel config for workaround
    Check /boot/config-$(uname -r) or /proc/config.gz for CONFIG_ARM64_WORKAROUND_REPEAT_TLBI or similar errata enablement option
    Affected if The kernel configuration does not have the workaround enabled or compiled in
  4. Confirm runtime errata status
    Check /sys/devices/system/cpu/cpu0/flags or similar (on some distros) or review dmesg for 'TLBI' or 'errata' messages at boot; also check if 'cat /proc/sys/abi/vsyscall' reveals anything Arm-specific, though the primary check is dmesg for errata notices
    Affected if Dmesg or system logs show the CPU is affected by the TLBI errata and no workaround is active
  5. Verify memory ordering behavior
    For deep inspection, run memory barrier stress tests or latency benchmarks that exercise TLBI;DSB sequences; if tests show unexpected memory ordering, the system may be affected
    Affected if Tests reveal stale data reads or memory ordering anomalies consistent with the described errata

The system is affected if it uses an Arm CPU impacted by this errata AND the running kernel does not have the ARM64_WORKAROUND_REPEAT_TLBI workaround enabled or compiled in.

Generated from the published advisory. Verify against your own configuration.

Check your environment

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AI-assisted, checked against the advisory. Informational, not a guarantee.

Remediation Closing itWhat it takes to close this. Where a vendor fix exists we point at it; where none exists we say so plainly, and can build one. Effort estimates are scoped from the advisory, not from your codebase.

From vendor data
Upgrade available Upgrade to 5.10.259 / 5.15.210 / 6.1.176 or later
Fixed in 5.10.2595.15.2106.1.176
Interim mitigation

Enable the ARM64_WORKAROUND_REPEAT_TLBI kernel workaround for affected Arm CPU models by updating the CPU errata detection logic in the Linux kernel, along with updating associated silicon errata documentation.

Fix this in Linux Kernel Scoped from the published advisory
  • Consultation2.0 h
  • Implementation4.0 h
  • Testing6.0 h
  • Review / QA2.0 h
14.0 hours of engineering $2,380
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References Go to the primary sourcePrimary sources — vendor advisories, patches and trackers. Where our summary and a reference disagree, the reference wins.

Primary sources

Practitioner notes

Contributed

Peer-ranked notes from engineers who’ve handled CVE-2026-53354 in production — separate from our analysis above.

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What this is

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What belongs here
  • Verified mitigations, workarounds, and config changes
  • Version or environment caveats, and links to real fixes
  • No weaponised exploit code, or anything meant to cause harm
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